The invention relates to a high speed instrumentation amplifier (IA) with minimized offset voltage and drift, particularly for signal amplification requiring very high speed and accuracy.
An instrumentation amplifier (IA) is a gain block having a pair of inputs for accurately amplifying an input signal applied thereacross. Conventional IAs include closed loop amplifiers each having gain determined by high accuracy resistors. The gain of the IAs is set by one or two external resistors. An inherent parasitic offset voltage is present between inputs of any IA and depends on temperature, represented by an offset drift, the level of the input signal, represented by a common mode rejection (CMR), and the frequency of the amplified input signal. Therefore, an error voltage present between the inputs of the IA is a momentary value of the offset voltage. The error voltage is generated in a number of stages of the IA by respective differential transistors, essentially due to a mismatch thereof.
Most common IAs incorporate three operational amplifiers and seven high accuracy resistors. The matching of the resistors must be precisely maintained over temperature and time in order to retain high gain accuracy and high CMR. Therefore, all resistors are formed with the integrated circuit, whereby the gain of the IA is selected by shorting respective terminals thereof. The gain is set by a single resistor Rg and is inversely proportional to the value thereof. Additional resistances such as of relays and sockets contribute to gain error as the value of Rg becomes small at high gains. The output impedance of the IA varies in a very wide range over frequency.
An optional offset adjustment is accomplished by means of a potentiometer coupled to additional terminals and affects only input stage components. Therefore, the null condition depends on the gain set. The offset voltage drift is affected by the amount of the offset voltage that is trimmed and cannot be nulled. Furthermore, the offset voltage and CMR adjustments are interactive and several iterations are required. Some IAs provide additional terminals for setting an ouput stage gain, output stage offset nulling, CMR trimming, etc. The offset performance is very difficult to maintain, especially at high gains. This may be caused by unequal temperature of input pins due to power dissipation of surrounding components. Air currents may result in rapid changes in the die temperature and thermocouple effects. Skirted heat sinks are used, although the IAs are predominantly low power devices.
Bipolar transistors are employed in the IA input stage as FETs are very difficult to match. The input stages with FETs also have a poor CMR which is further improved by an additional circuitry predetermining their drain-source voltage. The employment of the bipolar transistors results in relatively large input bias currents, wherein the transistors must operate at very low currents. A high circuit complexity further degrades an operational speed so that the conventional IAs are extremely slow.